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Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic., and . APCCAS, page 1720-1723. IEEE, (2008)Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption., and . Journal of Circuits, Systems, and Computers, 17 (6): 1173-1191 (2008)Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption., and . ICECS, page 845-848. IEEE, (2007)Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption., and . APCCAS, page 348-351. IEEE, (2008)Multi-Threshold Voltage FinFET Sequential Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 151-156 (2011)FinFET domino logic with independent gate keepers., and . Microelectron. J., 40 (11): 1531-1540 (2009)Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density., and . ICECS, page 443-446. IEEE, (2007)Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation., and . ISQED, page 855-860. IEEE Computer Society, (2008)Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew., and . ISQED, page 73-78. IEEE Computer Society, (2007)Dynamic wordline voltage swing for low leakage and stable static memory banks., and . ISCAS, page 1894-1897. IEEE, (2008)