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Active Memory Cube: A processing-in-memory architecture for exascale systems.

R. Nair, S. Antão, C. Bertolli, P. Bose, J. Brunheroto, T. Chen, C. Cher, C. Costa, J. Doi, C. Evangelinos, B. Fleischer, T. Fox, D. Gallo, L. Grinberg, J. Gunnels, A. Jacob, P. Jacob, H. Jacobson, T. Karkhanis, C. Kim, J. Moreno, J. O'Brien, M. Ohmacht, Y. Park, D. Prener, B. Rosenburg, K. Ryu, O. Sallenave, M. Serrano, P. Siegl, K. Sugavanam, and Z. Sura. IBM J. Res. Dev., (2015)

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Kevin W Fox

Thomas Fox

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An innovative low-power high-performance programmable signal processor for digital communications.J. Moreno, V. Zyuban, U. Shvadron, F. Neeser, J. Derby, M. Ware, K. Kailas, A. Zaks, A. Geva, S. Ben-David and 6 other author(s). IBM J. Res. Dev., 47 (2-3): 299-326 (2003)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.G. Ditlow, R. Montoye, S. Storino, S. Dance, S. Ehrenreich, B. Fleischer, T. Fox, K. Holmes, J. Mihara, Y. Nakamura and 4 other author(s). ISSCC, page 256-258. IEEE, (2011)Design methodology for semi custom processor cores.V. Zyuban, S. Asaad, T. Fox, A. Haen, D. Littrell, and J. Moreno. ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)

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Disambiguation of "Fox, Thomas W."

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Active Memory Cube: A processing-in-memory architecture for exascale systems.

Please choose a person to relate this publication to

Kevin W Fox

Thomas Fox

Thomas Fox

Thomas Fox

Thomas Fox

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Fox, Thomas W."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Active Memory Cube: A processing-in-memory architecture for exascale systems.

Please choose a person to relate this publication to

Kevin W Fox

Thomas Fox

Thomas Fox

Thomas Fox

Thomas Fox

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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Active Memory Cube: A processing-in-memory architecture for exascale systems.