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An innovative low-power high-performance programmable signal processor for digital communications., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 47 (2-3): 299-326 (2003)Near-Data Processing: Insights from a MICRO-46 Workshop., , , , , , and . IEEE Micro, 34 (4): 36-42 (2014)Scalable Instruction-Level Parallelism Through Tree-Instructions., and . International Conference on Supercomputing, page 1-11. ACM, (1997)Replication and Pipelining in Multiple-Instance Algorithms., and . ICPP, page 285-292. IEEE Computer Society Press, (1986)Comments on 'A systolic array for computing BA-1'., and . IEEE Trans. Acoust. Speech Signal Process., 37 (11): 1786-1789 (1989)Linear pseudosystolic array for partitioned matrix algorithms., , and . VLSI Signal Processing, 3 (3): 201-214 (1991)3D stacking of high-performance processors., , , , , , , , , and . HPCA, page 500-511. IEEE Computer Society, (2014)Preparation and optimization of a diverse workload for a large-scale heterogeneous system., , , , , , , , , and 69 other author(s). SC, page 32:1-32:17. ACM, (2019)A new look at exploiting data parallelism in embedded systems., and . CASES, page 159-169. ACM, (2003)Reducing instruction fetch energy with backwards branch control information and buffering., , , and . ISLPED, page 322-325. ACM, (2003)