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LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs.

, , , and . IEEE Comput. Archit. Lett., 16 (1): 42-45 (2017)

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Adaptive memory-side last-level GPU caching., , , , , and . ISCA, page 411-423. ACM, (2019)A Case for Specialized Processors for Scale-Out Workloads., , , , , , , , , and . IEEE Micro, 34 (3): 31-42 (2014)Architectural Support for Probabilistic Branches., , and . MICRO, page 108-120. IEEE Computer Society, (2018)Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors., , , , , , , , , and . ACM Trans. Comput. Syst., 30 (4): 15:1-15:24 (2012)Precise Runahead Execution., , , and . HPCA, page 397-410. IEEE, (2020)MDM: The GPU Memory Divergence Model., , , and . MICRO, page 1009-1021. IEEE, (2020)Scale-out processors, , , , , , , , , and . volume 40 of 3, IEEE Computer Society, (2012)Racing to Hardware-Validated Simulation., , , and . ISPASS, page 58-67. IEEE, (2019)Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores., , , and . IEEE Comput. Archit. Lett., 16 (1): 56-59 (2017)Scale-out processors., , , , , , , , , and 1 other author(s). ISCA, page 500-511. IEEE Computer Society, (2012)