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A brief survey on multispectral iris recognition., , and . IJAPR, 3 (4): 308-323 (2016)A Novel Approach to Accurate Timing Verification Using RTL Descriptions., and . DAC, page 638-641. ACM Press, (1989)Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits., , , , and . DAC, page 489-494. ACM Press, (1998)Iterative Wirability and Performance Improvement for FPGAs., and . DAC, page 321-325. ACM Press, (1993)Self-Healing Design in Deep Scaled CMOS Technologies., , , , and . Journal of Circuits, Systems, and Computers, (2012)Design in the nano-scale Era: Low-power, reliability, and error resiliency.. SoCC, page 445. IEEE, (2009)Data-retention flip-flops for power-down applications., and . ISCAS (2), page 677-680. IEEE, (2004)A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)Optimal Features Selection and Classification for Iris Recognition., and . IWCIA Special Track on Applications, page 113-123. Research Publishing, (2008)PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM., , , , , , , , , and . CoRR, (2019)