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A post-compiler approach to scratchpad mapping of code., , , , and . CASES, page 259-267. ACM, (2004)Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow., , and . Nano-Net, page 15. ICST/ACM, (2007)Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging., , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 12 (5): 968-981 (2018)Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips., , , , , , and . SoC, page 1-4. IEEE, (2006)Quest for the ultimate network-on-chip: the NaNoC project., , , , , , , , and . INA-OCMC@HiPEAC, page 43-46. ACM, (2012)Tackling the bottleneck of delay tables in 3D ultrasound imaging., , , , , , and . DATE, page 1683-1688. ACM, (2015)A Network Traffic Generator Model for Fast Network-on-Chip Simulation., , , , , and . DATE, page 780-785. IEEE Computer Society, (2005)Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer., , , , , , and . FPL, page 1-2. IEEE, (2016)A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 421-434 (2007)Area and Power Modeling Methodologies for Networks-on-Chip., , , , and . Nano-Net, page 1-7. IEEE, (2006)