( en | de | ru )

 

Disambiguation of "Yoneda, Tomokazu"

Author of the publication

copydeleteadd this publication to your clipboard
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

, , , and . Asian Test Symposium, page 306-311. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

 

Other publications of authors with the same name

Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions., , , and . ETS, page 1-6. IEEE, (2017)Test pattern selection to optimize delay test quality with a limited size of test set., , , , and . European Test Symposium, page 260. IEEE Computer Society, (2010)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , and . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing., , and . ATS, page 459-462. IEEE, (2007)Power-constrained test scheduling for multi-clock domain SoCs., , and . DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing., , , and . ISCAS, page 2942-2945. IEEE, (2007)An integrated DFT solution for power reduction in scan test applications by low power gating scan cell., , , , and . Integr., (2017)Test Pattern Ordering and Selection for High Quality Test Set under Constraints., , , and . IEICE Trans. Inf. Syst., 95-D (12): 3001-3009 (2012)A DFT Method for Time Expansion Model at Register Transfer Level., , and . DAC, page 682-687. IEEE, (2007)