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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Y. Xie, S. Eachempati, A. Yanamandra, V. Narayanan, and M. Irwin. NANOARCH, page 51-56. IEEE Computer Society, (2009)

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Soumya Senapati

Soumya Sarkar

Soumya Qbadou

Soumya Madhavan

Soumya Bera

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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.R. Das, S. Eachempati, A. Mishra, N. Vijaykrishnan, and C. Das. HPCA, page 175-186. IEEE Computer Society, (2009)RAFT: A router architecture with frequency tuning for on-chip networks.A. Mishra, A. Yanamandra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, and C. Das. J. Parallel Distributed Comput., 71 (5): 625-640 (2011)Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect.S. Eachempati, N. Vijaykrishnan, A. Nieuwoudt, and Y. Massoud. IET Circuits Devices Syst., 3 (2): 64-75 (2009)MIRA: A Multi-layered On-Chip Interconnect Router Architecture.D. Park, S. Eachempati, R. Das, A. Mishra, Y. Xie, N. Vijaykrishnan, and C. Das. ISCA, page 251-261. IEEE Computer Society, (2008)Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.Y. Xie, S. Eachempati, A. Yanamandra, V. Narayanan, and M. Irwin. NANOARCH, page 51-56. IEEE Computer Society, (2009)A case for dynamic frequency tuning in on-chip networks.A. Mishra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, and C. Das. MICRO, page 292-303. ACM, (2009)A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.Y. Chen, S. Eachempati, C. Wang, S. Datta, Y. Xie, and V. Narayanan. JETC, 9 (1): 5:1-5:20 (2013)Automated mapping for reconfigurable single-electron transistor arrays.Y. Chen, S. Eachempati, C. Wang, S. Datta, Y. Xie, and V. Narayanan. DAC, page 878-883. ACM, (2011)Optimizing power and performance for reliable on-chip networks.A. Yanamandra, S. Eachempati, N. Soundararajan, V. Narayanan, M. Irwin, and R. Krishnan. ASP-DAC, page 431-436. IEEE, (2010)Reconfigurable BDD based quantum circuits.S. Eachempati, V. Saripalli, N. Vijaykrishnan, and S. Datta. NANOARCH, page 61-67. IEEE Computer Society, (2008)

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Disambiguation of "Eachempati, Soumya"

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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Please choose a person to relate this publication to

Soumya Senapati

Soumya Sarkar

Soumya Qbadou

Soumya Madhavan

Soumya Bera

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Eachempati, Soumya"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

Please choose a person to relate this publication to

Soumya Senapati

Soumya Sarkar

Soumya Qbadou

Soumya Madhavan

Soumya Bera

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.