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Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

, , , , and . NANOARCH, page 51-56. IEEE Computer Society, (2009)

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Power-Area Trade-Offs in Divided Word Line Memory Arrays., , and . Journal of Circuits, Systems, and Computers, 7 (1): 49-68 (1997)Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)Using Memory Compression for Energy Reduction in an Embedded Java System., , , , and . Journal of Circuits, Systems, and Computers, 11 (5): 537-556 (2002)Exploring the Possibility of Operating in the Compressed Domain., , , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 507-515. Springer, (2004)A new optimization driven clustering algorithm for large circuits., , and . EURO-DAC, page 28-32. IEEE Computer Society, (1993)Multi-way FSM decomposition based on interconnect complexity., , and . EURO-DAC, page 390-395. IEEE Computer Society, (1993)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , and . IEEE Trans. Computers, 58 (7): 865-877 (2009)Digit Serial Multipliers., , and . J. Parallel Distributed Comput., 11 (2): 156-162 (1991)The design and implementation of the Arithmetic Cube II, a VLSI signal processing system., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 491-502 (1993)