( en | de | ru )

 

Disambiguation of "Alpert, Charles J."

Author of the publication

copydeleteadd this publication to your clipboard
Accurate estimation of global buffer delay within a floorplan.

, , , and . ICCAD, page 706-711. IEEE Computer Society / ACM, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Günther Alpert

Christian Alpert

Hansgünther Alpert

Thomas Alpert

Charles von J Russ

 

Other publications of authors with the same name

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique., , , , , , and . ISPD, page 104-109. ACM, (2002)Multilevel Circuit Partitioning., , and . DAC, page 530-533. ACM Press, (1997)GLARE: global and local wiring aware routability evaluation., , , , , , , , , and . DAC, page 768-773. ACM, (2012)A semi-persistent clustering technique for VLSI circuit placement., , , , and . ISPD, page 200-207. ACM, (2005)A fast algorithm for identifying good buffer insertion candidate locations., , and . ISPD, page 47-52. ACM, (2004)Accurate estimation of global buffer delay within a floorplan., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1140-1145 (2006)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Porosity-aware buffered Steiner tree construction., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 517-526 (2004)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)Effective free space management for cut-based placement via analytical constraint generation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (10): 1343-1353 (2003)