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Disambiguation of "George, Nithin"

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From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.

, , , , , , and . FPL, page 1-8. IEEE, (2015)

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George Mertzios

Combinatorial optimization and recognition of graph classes with applications to related models. TU Aachen, (2009)

Witold George

Hans George

George Glowik

George Leon

 

Other publications of authors with the same name

Virtualized Execution Runtime for FPGA Accelerators in the Cloud., , , , and . IEEE Access, (2017)SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs., , , , , , , , , and 6 other author(s). ICCAD, page 73:1-73:9. IEEE, (2020)Designing a virtual runtime for FPGA accelerators in the cloud., , , , and . FPL, page 1-2. IEEE, (2016)Automatic support for multi-module parallelism from computational patterns., , , , , , and . FPL, page 1-8. IEEE, (2015)Reducing the cost of floating-point mantissa alignment and normalization in FPGAs., , , , , and . FPGA, page 255-264. ACM, (2012)CodePin: An Instrumentation-Based Debug Tool of SYCLomatic., , , , and . IWOCL, page 16:1-16:2. ACM, (2024)FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages.. EPFL, Switzerland, (2016)Enriching C-based High-Level Synthesis with parallel pattern templates., , and . FPT, page 177-180. IEEE, (2016)Swarm and evolutionary computing algorithms for system identification and filter design: A comprehensive review., , , and . Swarm Evol. Comput., (2017)Nonlinear system identification using a cuckoo search optimized adaptive Hammerstein model., , and . Expert Syst. Appl., 42 (5): 2538-2546 (2015)