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Asynchronous CLS for Zero Crossing based Circuits., , and . ICECS, page 1025-1028. IEEE, (2010)A multiplexer-based digital passive linear counter (PLINCO)., , , and . ICECS, page 607-610. IEEE, (2009)The effect of correlated level shifting on noise performance in switched capacitor circuits., , , and . ISCAS, page 942-945. IEEE, (2012)A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion., , , , , , and . ISSCC, page 58-60. IEEE, (2019)Binary Access Memory: An optimized lookup table for successive approximation applications., , , , and . ISCAS, page 1620-1623. IEEE, (2011)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter., , , and . IEEE J. Solid State Circuits, 50 (5): 1203-1213 (2015)20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers., , , , and . ISSCC, page 356-357. IEEE, (2016)A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm., , , , , , and . ISSCC, page 68-70. IEEE, (2019)