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Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.

, , , , , , and . ISVLSI, page 212-217. IEEE Computer Society, (2016)

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Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices., , and . ISVLSI, page 615-620. IEEE Computer Society, (2017)A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering., , , , and . J. Hardw. Syst. Secur., 4 (2): 69-85 (2020)Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares., , and . IEEE Consumer Electronics Magazine, 7 (6): 15-22 (2018)Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS., , , , and . MWSCAS, page 1016-1019. IEEE, (2018)A Secure Integrity Checking System for Nanoelectronic Resistive RAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 416-429 (2019)Techniques for Improved Reliability in Memristive Crossbar PUF Circuits., , , , , , and . ISVLSI, page 212-217. IEEE Computer Society, (2016)Design for Eliminating Operation Specific Power Signatures from Digital Logic., , , , and . ACM Great Lakes Symposium on VLSI, page 111-116. ACM, (2019)Sneak path enabled authentication for memristive crossbar memories., , , and . AsianHOST, page 1-6. IEEE Computer Society, (2016)Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry., , , , , and . IET Comput. Digit. Tech., 12 (6): 297-305 (2018)Design Considerations for Memristive Crossbar Physical Unclonable Functions., , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 14 (1): 2:1-2:23 (2018)