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24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.

, , , , , , , , , , , and . ISQED, page 586-591. IEEE, (2012)

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 1175-1179 (2013)Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee., , and . ISSCC, page 298-299. IEEE, (2018)Misleading energy and performance claims in sub/near threshold digital systems., , , , , , , , , and 1 other author(s). ICCAD, page 625-631. IEEE, (2010)The circuit design of the synergistic processor element of a CELL processor., , , , , , , , , and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI., , , , , , , , , and 19 other author(s). IBM J. Res. Dev., 51 (5): 529-544 (2007)12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics., , , , , , and . ISLPED, page 163-168. IEEE/ACM, (2011)Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS., , , , , , and . ISLPED, page 21-26. IEEE/ACM, (2011)24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits., , , , , , , , , and 2 other author(s). ISQED, page 586-591. IEEE, (2012)13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO., , , , , , , and . ISSCC, page 486-488. IEEE, (2012)