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Disambiguation of "Kameyama, Michitaka"

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DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.

, , and . ISMVL, page 423-429. IEEE Computer Society, (2000)

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Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., and . ICRA, page 3691-3696. IEEE Computer Society, (1998)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 619-630 (2015)Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits., and . IEICE Trans. Inf. Syst., 93-D (8): 2126-2133 (2010)Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access., , and . IEICE Trans. Inf. Syst., 88-D (7): 1486-1491 (2005)Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (1): 342-351 (2011)Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates., , , and . IEICE Trans. Electron., 95-C (8): 1434-1443 (2012)