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Disambiguation of "Kar, Bapi"

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An early global routing framework for uniform wire distribution in SoCs.

, , and . SoCC, page 139-144. IEEE, (2016)

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Bapi Sarker

Sascha Bapistella

Ümit Bapisch

Halgurt Bapierre

Barbara Bapistella

 

Other publications of authors with the same name

A New Method for Defining Monotone Staircases in VLSI Floorplans., , and . ISVLSI, page 107-112. IEEE Computer Society, (2015)Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning., , and . CoRR, (2018)A Novel EPE Aware Hybrid Global Route Planner after Floorplanning., , and . VLSID, page 595-596. IEEE Computer Society, (2016)Live Demonstration: Autoencoder-Based Predictive Maintenance for IoT., , , , and . ISCAS, page 1. IEEE, (2019)ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (3): 913-926 (2020)A novel architecture for QPSK modulation based on time-mode signal processing., , and . VDAT, page 1-6. IEEE, (2014)A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring., , , , and . SSCI, page 1501-1507. IEEE, (2018)Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model., , and . CoRR, (2018)ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2518-2529 (2020)ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS., , , , , , and . CoRR, (2019)