( en | de | ru )

 

Disambiguation of "Gurrola-Navarro, Marco Antonio"

Author of the publication

copydeleteadd this publication to your clipboard
Design and validation of a mixed-signal correlator using a multiple-input floating gate transistor.

, , and . CCE, page 1-4. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Marco Antonio Mirata

Marco Antonio Delpiano

Salvador Navarro Navarro

Marco Antonio Chavarria Fabila

Giuseppe Antonio Di Marco

 

Other publications of authors with the same name

Experimental analysis of a transconductor-amplifier based on a mi-fgmos transistor., , and . CCE, page 1-4. IEEE, (2015)Design and validation of a mixed-signal correlator using a multiple-input floating gate transistor., , and . CCE, page 1-4. IEEE, (2015)Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels., , , , , , and . IEICE Electron. Express, 19 (11): 20220130 (2022)A technique to improve the transconductance in amplifiers., , , and . CCE, page 1-3. IEEE, (2016)A highly linear differential amplifier with tunable gain., , , and . CCE, page 1-5. IEEE, (2017)Approximations of the inverse wavelet transform for analogue circuits., , and . IEICE Electron. Express, 9 (24): 1823-1828 (2012)Binary sequence correlator using a MIFGMOS., , , and . IEICE Electron. Express, 13 (3): 20151061 (2016)Class AB Op-Amp With Accurate Static Current Control for Low and High Supply Voltages., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2775-2779 (2021)Impedance-mode capacitance multiplier with OTA-based flipped voltage follower for high accuracy and large multiplication factor., , , , , and . IEICE Electron. Express, 19 (19): 20220208 (2022)Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits., , , , , and . IEICE Electron. Express, 17 (3): 20190748 (2020)