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Disambiguation of "Pullini, Antonio"

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A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.

, , , , , and . ISCAS, page 2910. IEEE, (2016)

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Antonio Nuzzo

Antonio Galeano

Antonio Souto

Antonio Peter

Antonio Bergua

 

Other publications of authors with the same name

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI., , , , and . CoRR, (2020)Timing-Error-Tolerant Network-on-Chip Design Methodology., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (7): 1297-1310 (2007)Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis., , , , and . DATE, page 616-621. IEEE, (2009)Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 57 (1): 127-139 (2022)On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits., , , , , , and . ISCAS, page 2761-2764. IEEE, (2008)Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect., , , and . CoRR, (2020)An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding., , , , and . J. Low Power Electron., 14 (1): 101-109 (2018)Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology., , , , , , and . ACM Great Lakes Symposium on VLSI, page 501-504. ACM, (2007)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)