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Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications.

, , , , and . J. Low Power Electron., 11 (3): 333-339 (2015)

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Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC., , , , and . VDAT, page 1-6. IEEE, (2016)A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage., , and . ISED, page 1-4. IEEE, (2017)Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications., , , , and . J. Low Power Electron., 11 (3): 333-339 (2015)CAD-Based Analysis of Power Distribution Network for SOC Design., , , and . ACSS (1), volume 396 of Advances in Intelligent Systems and Computing, page 189-198. Springer, (2015)Analysis of power distribution network for some cryptocores., , , and . ICACCI, page 2618-2622. IEEE, (2014)A CAD approach for pre-layout optimal PDN design and its post-layout verification., , , and . Microprocess. Microsystems, (2019)Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores., , , , and . FICTA (2), volume 328 of Advances in Intelligent Systems and Computing, page 13-20. Springer, (2014)An Performance Analysis of RSA Scheme Using Artificial Neural Network., , , and . ICCCNT, page 1-5. IEEE, (2018)