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Disambiguation of "Jr., James H. Mulligan"

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Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.

, , and . ISCAS, page 1748-1751. IEEE, (1995)

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Other publications of authors with the same name

Clock frequency and latency in synchronous digital systems., and . IEEE Trans. Signal Process., 39 (4): 930-934 (1991)A Figure of Merit for Single-Pass Data Recording Systems.. IRE Trans. Electron. Comput., 8 (1): 48-54 (1959)Two coding strategies for bidirectional associative memory., , and . IEEE Trans. Neural Networks, 1 (1): 81-92 (1990)Incorporating interconnect, register, and clock distribution delays into the retiming process., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (1): 105-120 (1997)Integration of Clock Skew and Register Delays into a Retiming Algorithm., , and . ISCAS, page 1483-1486. IEEE, (1993)On multiple training for bidirectional associative memory., , and . IEEE Trans. Neural Networks, 1 (3): 275-276 (1990)Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay., , and . ISCAS, page 1748-1751. IEEE, (1995)Multiple training concept for back-propagation neural networks for use in associative memories., , and . Neural Networks, 6 (8): 1169-1175 (1993)Optimization of phase-locked loop performance in data recovery systems., and . IEEE J. Solid State Circuits, 29 (9): 1022-1034 (September 1994)Guaranteed recall of all training pairs for bidirectional associative memory., , and . IEEE Trans. Neural Networks, 2 (6): 559-567 (1991)