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A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.

, , , , , , , and . IEEE Trans. Computers, 66 (8): 1293-1301 (2017)

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A novel DFT architecture for 3DIC test, diagnosis and repair., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A 4-GHz universal high-frequency on-chip testing platform for IP validation., , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2014)A Built-Off Self-Repair Scheme for Channel-Based 3D Memories., , , , , , , and . IEEE Trans. Computers, 66 (8): 1293-1301 (2017)A Local Parallel Search Approach for Memory Failure Pattern Identification., , , , , and . IEEE Trans. Computers, 65 (3): 770-780 (2016)Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement., , , , , , and . IEEE Des. Test, 33 (2): 30-39 (2016)Redundancy architectures for channel-based 3D DRAM yield improvement., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2014)On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs., , , , , and . IEEE Des. Test, 31 (4): 16-26 (2014)A memory yield improvement scheme combining built-in self-repair and error correction codes., , , , , , , , , and . ITC, page 1-9. IEEE Computer Society, (2012)Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package., , , , , , , and . IEEE Des. Test, 34 (3): 50-58 (2017)Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)