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CAD Directions for High Performance Asynchronous Circuits., , , , , , and . DAC, page 116-121. ACM Press, (1999)Preface., , , and . Electron. Notes Theor. Comput. Sci., 146 (2): 1-3 (2006)Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits., , , , , , , and . ASYNC, page 80-. IEEE Computer Society, (1998)Synthesis of asynchronous control circuits with automatically generated relative timing assumptions., , , and . ICCAD, page 324-331. IEEE Computer Society, (1999)Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems., and . IET Comput. Digit. Tech., 5 (4): 316-317 (2011)Relative timing asynchronous design., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 129-140 (2003)Guest Editors' Introduction: GALS Design and Validation., , and . IEEE Des. Test Comput., 24 (5): 414-416 (2007)Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (2): 109-130 (2002)Automatic synthesis of computation interference constraints for relative timing verification., and . ICCD, page 16-22. IEEE Computer Society, (2009)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)