( en | de | ru )

 

Disambiguation of "Srinivasa, Srivatsa Rangachar"

Author of the publication

copydeleteadd this publication to your clipboard
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.

, , , , , , , , and . ISVLSI, page 128-133. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Srinivasa Marimganti

Srinivasa Thimmaiah

Srinivasa Subramaniam

Srinath Srinivasa

Sundaravaradan Srinivasa Rangachari

 

Other publications of authors with the same name

Cryogenic Memory Technologies., , , and . CoRR, (2021)Emerging reconfigurable nanotechnologies: can they support future electronics?, , , , , , , and . ICCAD, page 13. ACM, (2018)Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems., , , , , , , , , and 1 other author(s). ISQED, page 1-4. IEEE, (2022)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support., , , , , , , , , and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding., , , , , , , , and . DATE, page 1400-1403. IEEE, (2021)A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs., , , , and . ISVLSI, page 22-27. IEEE Computer Society, (2018)On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1603-1613 (October 2023)Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs., , , , , and . ISCAS, page 1-5. IEEE, (2019)ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2533-2545 (2019)