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Disambiguation of "Gupta, Sandeep K."

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Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors.

, , and . DATE, page 927-932. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Sandeep Gupta

Varun K Gupta

Sandeep Sadanandan

Sandeep Ameta

Sandeep Nambiar

 

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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture., , and . IEEE J. Solid State Circuits, 41 (12): 2650-2657 (2006)Test Generation for Weak Resistive Bridges., , and . ATS, page 265-272. IEEE, (2006)Path delay fault diagnosis in combinational circuits with implicitfault enumeration., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (10): 1226-1235 (2001)LT-RTPG: a new test-per-scan BIST TPG for low switching activity., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (8): 1565-1574 (2006)Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa., and . IEEE Trans. Computers, 45 (1): 63-73 (1996)Optimizing redundancy design for chip-multiprocessors for flexible utility functions., and . ITC, page 1-8. IEEE Computer Society, (2014)Design and test of latch-based circuits to maximize performance, yield, and delay test quality., and . ITC, page 94-103. IEEE Computer Society, (2010)ERTG: A test generator for error-rate testing., and . ITC, page 1-10. IEEE Computer Society, (2007)Switch-level delay test of domino logic circuits., , and . ITC, page 367-376. IEEE Computer Society, (2001)BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level., and . Asian Test Symposium, page 244-252. IEEE Computer Society, (1998)