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Dedicated technology threshold voltage tuning for 6T SRAM beyond N7., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)Hardware-Based Aging Mitigation Scheme for Memory Address Decoder., , , , , , and . ETS, page 1-6. IEEE, (2019)Mitigation of Sense Amplifier Degradation Using Skewed Design., , , , , and . DATE, page 1614-1617. IEEE, (2020)Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7., , , , , , , , , and 2 other author(s). ESSDERC, page 256-259. IEEE, (2017)STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance., , , , , and . NVMSA, page 1-6. IEEE, (2015)Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM., , , , , and . DATE, page 1042-1047. IEEE, (2012)A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link., , and . IEEE J. Solid State Circuits, 47 (7): 1784-1796 (2012)Methodology for Application-Dependent Degradation Analysis of Memory Timing., , , , , , and . DATE, page 162-167. IEEE, (2019)Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write., , , , and . ESSDERC, page 282-285. IEEE, (2012)A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers., , and . IEEE J. Solid State Circuits, 44 (7): 2065-2077 (2009)