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Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism.

, , , , and . J. Electron. Test., 26 (4): 453-464 (2010)

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An Industrial Approach to Core-Based System Chip Testing.. VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 389-400. Kluwer, (2001)How Useful are the ITC 02 SoC Test Benchmarks?, and . IEEE Des. Test Comput., 19 (5): 120, 119 (2002)Application of Deterministic Logic BIST on Industrial Circuits., , , and . J. Electron. Test., 17 (3-4): 351-362 (2001)Optimal Interconnect ATPG Under a Ground-Bounce Constraint., , and . J. Electron. Test., 21 (1): 17-31 (2005)Editorial., and . IET Comput. Digit. Tech., 1 (3): 145 (2007)Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis., and . IEEE Des. Test Comput., 25 (3): 206-207 (2008)Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint., , , and . IEEE Des. Test Comput., 20 (2): 8-18 (2003)Conference Reports., , , , , and . IEEE Des. Test Comput., 23 (4): 262-265 (2006)Testing Embedded-Core-Based System Chips., , and . Computer, 32 (6): 52-60 (1999)SOC test architecture design for efficient utilization of test bandwidth., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 399-429 (2003)