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Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.

, , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)

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Code Coverage-Based Power Estimation Techniques for Microprocessors., , , and . Journal of Circuits, Systems, and Computers, 11 (5): 557- (2002)Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips., , , , , , , , , and . IEEE Micro, 31 (6): 6-18 (2011)A fine-grain dynamic sleep control scheme in MIPS R3000., , , , , , , , , and 7 other author(s). ICCD, page 612-617. IEEE Computer Society, (2008)Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs., , , , , and . NOCS, page 61-68. IEEE Computer Society, (2010)Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor., and . NVMSA, page 1-6. IEEE, (2017)Delay modeling and static timing analysis for MTCMOS circuits., and . ASP-DAC, page 570-575. IEEE, (2006)Overview on Low Power SoC Design Technology.. ASP-DAC, page 634-636. IEEE Computer Society, (2007)Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , and 7 other author(s). ASP-DAC, page 87-88. IEEE, (2011)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Datapath Generator Based on Gate-Level Symbolic Layout., , , , , and . DAC, page 388-393. IEEE Computer Society Press, (1990)