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A Fused Floating-Point Four-Term Dot Product Unit.

, and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (3): 370-378 (2016)

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A Fused Floating-Point Three-Term Adder., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 2842-2850 (2014)A low-power dual-path floating-point fused add-subtract unit., , and . ACSCC, page 998-1002. IEEE, (2012)Enhanced Floating-Point Adder with Full Denormal Support., , , and . ARITH, page 1-8. IEEE, (2022)A Fused Floating-Point Four-Term Dot Product Unit., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (3): 370-378 (2016)Improved Architectures for a Fused Floating-Point Add-Subtract Unit., and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2285-2291 (2012)Improved Architectures for a Floating-Point Fused Dot Product Unit., and . IEEE Symposium on Computer Arithmetic, page 41-48. IEEE Computer Society, (2013)Enhanced Floating-Point Multiply-Add with Full Denormal Support., , , and . ARITH, page 143-150. IEEE, (2023)