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Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures., , , , and . IEEE Trans. Computers, 54 (8): 1025-1040 (2005)Energy reduction through crosstalk avoidance coding in networks on chip., , , and . J. Syst. Archit., 54 (3-4): 441-451 (2008)Crosstalk-aware Energy Reduction in NoC Communication Fabrics., , , and . SoCC, page 225-228. IEEE, (2006)Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs., , , and . ACM Great Lakes Symposium on VLSI, page 192-195. ACM, (2004)Communication Aware Recovery Configurations for Networks-on-Chip., , and . IOLTS, page 201-206. IEEE Computer Society, (2008)Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding., , , and . ISVLSI, page 317-324. IEEE Computer Society, (2007)Design, Synthesis, and Test of Networks on Chips., , , , and . IEEE Des. Test Comput., 22 (5): 404-413 (2005)Design of a switch for network on chip applications., , , and . ISCAS (5), page 217-220. IEEE, (2003)BIST for Network-on-Chip Interconnect Infrastructures., , , and . VTS, page 30-35. IEEE Computer Society, (2006)Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics., , , and . IOLTS, page 161-166. IEEE Computer Society, (2007)