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Disambiguation of "Mai, Ken"

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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.

, , , , , , and . Proc. IEEE, 96 (2): 343-365 (2008)

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Ken Lau

Ken Endo

Ken Herrmann

Ken Heydolph

Ken Eckstein

 

Other publications of authors with the same name

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS., , , , , and . A-SSCC, page 1-4. IEEE, (2015)Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines., , , , , and . CICC, page 415-418. IEEE, (2008)ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 2 (2): 15:1-15:32 (2009)An efficient reliable PUF-based cryptographic key generator in 65nm CMOS., and . DATE, page 1-6. European Design and Automation Association, (2014)A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement., and . IACR Cryptology ePrint Archive, (2015)Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing., , , , and . FPGA, page 139-142. ACM, (2012)Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS., , , , , , and . IEEE J. Solid State Circuits, 40 (1): 261-275 (2005)Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC., , , , , and . PRDC, page 98-107. IEEE Computer Society, (2013)Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers., , and . HOST, page 7-13. IEEE Computer Society, (2015)A DPA-resistant self-timed three-phase dual-rail pre-charge logic family., , , and . HOST, page 112-117. IEEE Computer Society, (2015)