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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.

, , , , , , and . Proc. IEEE, 96 (2): 343-365 (2008)

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Analog Circuit and Layout Synthesis Revisited.. ISPD, page 83. ACM, (2015)Multiprocessor-based placement by simulated annealing., and . DAC, page 567-573. IEEE Computer Society Press, (1986)A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC., , , , and . DAC, page 1-6. ACM, (2000)An O(n) Algorithm for Transistor Stacking with Performance Constraints., and . DAC, page 221-226. ACM Press, (1996)FPGA routing and routability estimation via Boolean satisfiability., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (2): 222-231 (1998)Device-level early floorplanning algorithms for RF circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (4): 375-388 (1999)Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1814-1827 (2011)Integer programming based topology selection of cell-level analog circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (4): 401-412 (1995)Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (6): 703-717 (2000)Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters, , , , , and . CoRR, (2007)