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Disambiguation of "Kashiwabara, Toshinobu"

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Approximate Model Checking Using a Subset of First-order Logic.

, , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)

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Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition., , and . IEICE Trans. Inf. Syst., 89-D (3): 1120-1127 (2006)Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas., , and . ATVA, volume 3299 of Lecture Notes in Computer Science, page 108-119. Springer, (2004)Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2778-2789 (2007)Checker Generation of Assertions with Local Variables for Model Checking., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Approximate Model Checking Using a Subset of First-order Logic., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)On Minimal Augmentation of a Graph to Obtain an Interval Graph., , , and . J. Comput. Syst. Sci., 22 (1): 60-97 (1981)Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic., , and . ATVA, volume 5311 of Lecture Notes in Computer Science, page 318-331. Springer, (2008)Automatic monitor generation from regular expression based specifications for module interface verification., , , and . ISCAS (4), page 3555-3558. IEEE, (2005)Crossing Minimization in Linear Embeddings of Graphs., , , and . IEEE Trans. Computers, 39 (1): 124-127 (1990)