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An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz., , , , , , , , , and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate., , and . IEEE Access, (2020)Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing., , , , , , , , and . Proc. IEEE, 104 (10): 1844-1863 (2016)Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3., , and . Neural Comput. Appl., 35 (15): 11013-11041 (May 2023)Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT., , , , and . IEEE Trans. Ind. Informatics, 18 (5): 3055-3065 (2022)A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching., , and . ISOCC, page 203-206. IEEE, (2011)Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 56 (4): 1116-1128 (2021)Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application., , and . IEEE Access, (2020)From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society., , and . IEEE Trans. Ind. Informatics, 19 (8): 8953-8964 (August 2023)An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications., , and . ISCAS, page 1248-1251. IEEE, (2013)