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Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

A. Ferraiuolo, Y. Wang, D. Zhang, A. Myers, and G. Suh. HPCA, page 382-393. IEEE Computer Society, (2016)

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Andrew Singer

Andrew Torda

Andrew Cato

Andrew Huvos

Andrew Lee

Other publications of authors with the same name

SecDCP: secure dynamic cache partitioning for efficient timing channel protection.Y. Wang, A. Ferraiuolo, D. Zhang, A. Myers, and G. Suh. DAC, page 74:1-74:6. ACM, (2016)Detection of trojans using a combined ring oscillator network and off-chip transient power analysis.X. Zhang, A. Ferraiuolo, and M. Tehranipoor. JETC, 9 (3): 25:1-25:20 (2013)Policy Transparency: Authorization Logic Meets General Transparency to Prove Software Supply Chain Integrity.A. Ferraiuolo, R. Behjati, T. Santoro, and B. Laurie. SCORED@CCS, page 3-13. ACM, (2022)Timing channel protection for a shared memory controller.Y. Wang, A. Ferraiuolo, and G. Suh. HPCA, page 225-236. IEEE Computer Society, (2014)Low-overhead and high coverage run-time race detection through selective meta-data management.R. Huang, E. Halberg, A. Ferraiuolo, and G. Suh. HPCA, page 96-107. IEEE Computer Society, (2014)Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.A. Ferraiuolo, Y. Wang, D. Zhang, A. Myers, and G. Suh. HPCA, page 382-393. IEEE Computer Society, (2016)Secure Information Flow Verification with Mutable Dependent Types.A. Ferraiuolo, W. Hua, A. Myers, and G. Suh. DAC, page 6:1-6:6. ACM, (2017)Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC.A. Ferraiuolo, X. Zhang, and M. Tehranipoor. ICCAD, page 37-42. ACM, (2012)Komodo: Using verification to disentangle secure-enclave hardware from software.A. Ferraiuolo, A. Baumann, C. Hawblitzel, and B. Parno. SOSP, page 287-305. ACM, (2017)Detecting Hardware Trojans using On-chip Sensors in an ASIC Design.S. Kelly, X. Zhang, M. Tehranipoor, and A. Ferraiuolo. J. Electron. Test., 31 (1): 11-26 (2015)

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Disambiguation of "Ferraiuolo, Andrew"

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Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

Please choose a person to relate this publication to

Andrew Singer

Andrew Torda

Andrew Cato

Andrew Huvos

Andrew Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ferraiuolo, Andrew"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

Please choose a person to relate this publication to

Andrew Singer

Andrew Torda

Andrew Cato

Andrew Huvos

Andrew Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.