Author of the publication

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.

, , , , , and . ASP-DAC, page 255-260. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA., , and . ISLPED, page 3-8. IEEE/ACM, (2011)A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary., , and . ISSCC, page 404-405. IEEE, (2010)One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects., , and . VLSI Design, 6 (1-4): 65-67 (1998)Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply., , and . IEICE Trans. Electron., 89-C (3): 364-369 (2006)A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring., , , and . IEICE Trans. Electron., 100-C (9): 736-745 (2017)Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3485-3491 (2005)A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging., , and . IEICE Trans. Electron., 94-C (10): 1626-1633 (2011)All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter., , , , and . IEICE Trans. Electron., 94-C (4): 487-494 (2011)A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications., and . IEICE Trans. Electron., 100-C (12): 1078-1086 (2017)Cascaded Time Difference Amplifier with Differential Logic Delay Cell., , , , and . IEICE Trans. Electron., 94-C (4): 654-662 (2011)