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A 3D mixed-mode ESD protection circuit simulation-design methodology.

H. Xie, R. Zhan, H. Feng, G. Chen, A. Wang, and R. Gafiteanu. CICC, page 243-246. IEEE, (2004)

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Yühe Feng

Feng Yan

Feng Shi

Feng Qiu

Feng Li

Other publications of authors with the same name

L-simulator: a magPEEC-based new CAD tool for simulating magnetic-enhanced IC inductors of 3D arbitrary geometry.H. Long, Z. Feng, H. Feng, A. Wang, and T. Ren. ISCAS (5), page 233-237. IEEE, (2004)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism.R. Zhan, H. Feng, H. Xie, and A. Wang. ISCAS (5), page 217-220. IEEE, (2004)A mixed-mode ESD protection circuit simulation-design methodology.H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, A. Wang, and R. Gafiteanu. IEEE J. Solid State Circuits, 38 (6): 995-1006 (2003)A 600 MHz-BW 154.3 dB-FoM current-mode continuous-time pipelined ADC in 12 nm CMOS.X. Xing, H. Liang, X. Shang, Z. Yang, H. Feng, J. Hu, Y. Huang, J. Dong, J. Li, and Y. Wang. Microelectron. J., (December 2023)A Low Frequency Drift LC-DCO with Wide Temperature Range.J. Hu, S. Fang, H. Feng, X. Xing, H. Wang, and L. Yang. ICTA, page 121-122. IEEE, (2022)An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS.Z. Yang, X. Xing, X. Zheng, H. Feng, H. Fu, and G. Gielen. APCCAS, page 181-184. IEEE, (2022)A 4 to 5GHz Digitally Controlled Ring Oscillator with 100kHz Resolution using Noise Cancellation Technology in 40nm CMOS.S. Fang, J. Hu, H. Feng, X. Xing, H. Wang, and L. Yang. ICTA, page 110-111. IEEE, (2022)An ESD protection circuit for mixed-signal ICs.H. Feng, K. Gong, and A. Wang. CICC, page 493-496. IEEE, (2001)ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress.R. Zhan, H. Xie, H. Feng, and A. Wang. ASP-DAC, page 79-82. ACM Press, (2005)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism.R. Zhan, H. Feng, Q. Wu, H. Xie, X. Guan, G. Chen, and A. Wang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1421-1428 (2004)

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Disambiguation of "Feng, Haigang"

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A 3D mixed-mode ESD protection circuit simulation-design methodology.

Please choose a person to relate this publication to

Yühe Feng

Feng Yan

Feng Shi

Feng Qiu

Feng Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Feng, Haigang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3D mixed-mode ESD protection circuit simulation-design methodology.

Please choose a person to relate this publication to

Yühe Feng

Feng Yan

Feng Shi

Feng Qiu

Feng Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 3D mixed-mode ESD protection circuit simulation-design methodology.