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Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling.

, , , and . ASPLOS, page 723-736. ACM, (2017)

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SimpleSSD: Modeling Solid State Drives for Holistic System Simulation., , , , , , , and . IEEE Comput. Archit. Lett., 17 (1): 37-41 (2018)Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors., , and . ICCD, page 84-91. IEEE Computer Society, (2010)EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors., , , , , , , and . ISLPED, page 303-306. ACM, (2014)SCOOP: A Scalable Object-Oriented Serverless Platform., , , and . CLOUD, page 1-3. IEEE, (2023)Storage consolidation: Not always a panacea, but can we ease the pain?, , , , and . ISPASS, page 159-160. IEEE Computer Society, (2016)Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors., , and . J. Low Power Electron., 8 (5): 624-635 (2012)CachedGC: Cache-Assisted Garbage Collection in Modern Solid State Drives., and . MASCOTS, page 79-86. IEEE Computer Society, (2018)Cross-Platform Performance Evaluation of Stateful Serverless Workflows., , and . IISWC, page 63-73. IEEE, (2021)Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling., , , and . ASPLOS, page 723-736. ACM, (2017)Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors., , and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 211-221. Springer, (2010)