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A Multi-GPU Implementation of a D2Q37 Lattice Boltzmann Code., , , , , , , , and . PPAM (1), volume 7203 of Lecture Notes in Computer Science, page 640-650. Springer, (2011)Simulating spin systems on IANUS, an FPGA-based computer., , , , , , , , , and 8 other author(s). Comput. Phys. Commun., 178 (3): 208-216 (2008)Runtime mechanisms to survive new HPC architectures: A use case in human respiratory simulations., , , , and . Int. J. High Perform. Comput. Appl., (2020)Compressed Real Numbers for AI: a case-study using a RISC-V CPU., , , , , , , and . CoRR, (2023)HPCG on long-vector architectures: Evaluation and optimization on NEC SX-Aurora and RISC-V., , , and . Future Gener. Comput. Syst., (June 2023)A portable coding strategy to exploit vectorization on combustion simulations., , , , , , and . CoRR, (2022)Accelerating FFT Using NEC SX-Aurora Vector Engine., , and . Euro-Par Workshops, volume 13098 of Lecture Notes in Computer Science, page 179-190. Springer, (2021)NVIDIA Grace Superchip Early Evaluation for HPC Applications., , , , , , , and . HPC Asia Workshops, page 45-54. ACM, (2024)Open-Source Shared Memory implementation of the HPCG benchmark: analysis, improvements and evaluation on Cavium ThunderX2., , , , and . HPCS, page 225-232. IEEE, (2019)Design Space Exploration of Next-Generation HPC Machines., , , , , and . IPDPS, page 54-65. IEEE, (2019)