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Disambiguation of "Shin, Youngsoo"

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Placement optimization for MP-DSAL compliant layout.

, , and . ICICDT, page 1-4. IEEE, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)

Hyung-Uk Shin

Ikuya Shinoda

Syng-Hwan Shin

 

Other publications of authors with the same name

Power-gating-aware high-level synthesis., , , and . ISLPED, page 39-44. ACM, (2008)Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation., , and . ASP-DAC, page 629-634. IEEE, (2008)Automatic insertion of airgap with design rule constraints., and . ASP-DAC, page 381-386. IEEE, (2018)Optimization of Machine Learning Guided Optical Proximity Correction., , and . MWSCAS, page 921-924. IEEE, (2018)Redundant Via insertion in SADP process with cut merging and optimization., , and . VLSI-SoC, page 1-6. IEEE, (2017)Design and Optimization of Multiple-Mesh Clock Network., , and . VLSI-SoC (Selected Papers), volume 464 of IFIP Advances in Information and Communication Technology, page 39-57. Springer, (2014)Introducing irregularity to routing architecture of structured ASIC for better routability., , and . FPT, page 224-228. IEEE, (2012)Endurance Enhancement of Multi-Level Cell Phase Change Memory., , and . ICCAD, page 1-8. ACM, (2019)Clock Gating Synthesis of Pulsed-Latch Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (7): 1019-1030 (2012)Pulsed-Latch Aware Placement for Timing-Integrity Optimization., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1856-1869 (2011)