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Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations.

D. Juan, S. Garg, and D. Marculescu. DATE, page 383-388. IEEE, (2011)

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Neil Garg

Siddharth Kaza

Siddharth Nanguneri

Siddharth Hegde

Siddharth Ray

Other publications of authors with the same name

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip.C. Ravishankar, S. Ananthanarayanan, S. Garg, and A. Kennings. FPL, page 41-48. IEEE, (2012)BandiTS: Dynamic timing speculation using multi-armed bandit based optimization.J. Zhang, and S. Garg. DATE, page 922-925. IEEE, (2017)Low cost permanent fault detection using ultra-reduced instruction set co-processors.S. Ananthanarayanan, S. Garg, and H. Patel. DATE, page 933-938. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Fragility of the Commons under Prospect-Theoretic Risk Attitudes.A. Hota, S. Garg, and S. Sundaram. CoRR, (2014)HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors.Y. Turakhia, B. Raghunathan, S. Garg, and D. Marculescu. DAC, page 173:1-173:7. ACM, (2013)Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements.C. O'Sullivan, P. Levine, and S. Garg. ISQED, page 96-103. IEEE, (2013)Exploiting Process Variability in Voltage/Frequency Control.S. Herbert, S. Garg, and D. Marculescu. IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1392-1404 (2012)Adversarially Robust Learning via Entropic Regularization.G. Jagatap, A. Chowdhury, S. Garg, and C. Hegde. CoRR, (2020)Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators.J. Zhang, K. Rangineni, Z. Ghodsi, and S. Garg. DAC, page 19:1-19:6. ACM, (2018)Outsourcing Private Machine Learning via Lightweight Secure Arithmetic Computation.S. Garg, Z. Ghodsi, C. Hazay, Y. Ishai, A. Marcedone, and M. Venkitasubramaniam. CoRR, (2018)

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Disambiguation of "Garg, Siddharth"

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Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations.

Please choose a person to relate this publication to

Neil Garg

Siddharth Kaza

Siddharth Nanguneri

Siddharth Hegde

Siddharth Ray

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Garg, Siddharth"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations.

Please choose a person to relate this publication to

Neil Garg

Siddharth Kaza

Siddharth Nanguneri

Siddharth Hegde

Siddharth Ray

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations.