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Disambiguation of "Ichihara, Hideyuki"

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An FPGA-based fail-soft system with adaptive reconfiguration.

, , , , and . IOLTS, page 127-132. IEEE Computer Society, (2010)

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Hideyuki Sakamoto

 

Other publications of authors with the same name

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis., , , and . ITC-Asia, page 55-60. IEEE, (2019)A Practical Threshold Test Generation for Error Tolerant Application., , , and . IEICE Trans. Inf. Syst., 93-D (10): 2776-2782 (2010)Test cost reduction for logic circuits: Reduction of test data volume and test application time., , , and . Syst. Comput. Jpn., 36 (6): 69-83 (2005)Test Compression Based on Lossy Image Encoding., , , and . Asian Test Symposium, page 273-278. IEEE Computer Society, (2011)Dynamic Test Compression Using Statistical Coding., , , and . Asian Test Symposium, page 143-. IEEE Computer Society, (2001)On Test Generation with A Limited Number of Tests., , and . Great Lakes Symposium on VLSI, page 12-15. IEEE Computer Society, (1999)Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs., , , and . VLSI Design, page 329-334. IEEE Computer Society, (2003)A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing., , and . DFT, page 1-6. IEEE, (2021)An Architecture of Embedded Decompressor with Reconfigurability for Test Compression., , and . IEICE Trans. Inf. Syst., 91-D (3): 713-719 (2008)A Resource Estimation Method in Multi-Cloud Environment with a Model Based on a Repairable-Item Inventory System., , , and . COMPSAC, page 1113-1120. IEEE, (2023)