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Gate array implementation of on-line algorithms for floating-point operations., and . VLSI Signal Processing, 3 (4): 307-317 (1991)Implementing division with field programmable gate arrays., and . VLSI Signal Processing, 7 (3): 271-285 (1994)A FPGA-based Library for On-Line Signal Processing., , , and . VLSI Signal Processing, 28 (1-2): 129-143 (2001)Very-High Radix Division with Prescaling and Selection by Rounding., , and . IEEE Trans. Computers, 43 (8): 909-918 (1994)Radix-4 energy efficient carry-free truncated multiplier., and . ACSSC, page 1596-1600. IEEE, (2016)Sign detection and comparison networks with a small number of transitions., and . IEEE Symposium on Computer Arithmetic, page 59-66. IEEE Computer Society, (1995)High-Performance Left-to-Right Array Multiplier Design., and . IEEE Symposium on Computer Arithmetic, page 4-11. IEEE Computer Society, (2003)ALIAS Environment: A Design Tool for Application Specific Arrays., and . SPDP, page 504-511. IEEE Computer Society, (1993)Combining leak-resistant arithmetic for elliptic curves defined over Fp and RNS representation., , and . IACR Cryptology ePrint Archive, (2010)Radix-16 Evaluation of Certain Elementary Functions.. IEEE Trans. Computers, 22 (6): 561-566 (1973)