( en | de | ru )

 

Disambiguation of "Chan, Cheong-Fat"

Author of the publication

copydeleteadd this publication to your clipboard
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver.

, , and . ISCAS, page 307-310. IEEE, (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Eunhae Cheong

Eun Cheong

Chul Cheong

Kit Cheong

Wilhelm Chan

 

Other publications of authors with the same name

A four-phase handshaking asynchronous static RAM design for self-timed systems., , and . IEEE J. Solid State Circuits, 34 (1): 90-96 (1999)Asynchronous cross-pipelined multiplier., , , and . IEEE J. Solid State Circuits, 36 (8): 1272-1275 (2001)A high-efficiency strongly self-checking asynchronous datapath., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1484-1494 (2004)A New Control Circuit for Asynchronous Micropipelines., , , and . IEEE Trans. Computers, 50 (9): 992-997 (2001)Preparing smartcard for the future: from passive to active., , , and . IEEE Trans. Consumer Electron., 50 (1): 245-250 (2004)High speed CMOS digital-to-analog converter with linear interpolator., , and . IEEE Trans. Consumer Electron., 46 (4): 1137-1142 (2000)An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 254-256 (2004)A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (7): 653-657 (2008)Pipelined Dataflow Architecture of a Small Processor., , , , , , and . PDPTA, page 1217-1223. CSREA Press, (1999)A 900 MHz 1.2 V CMOS mixer with high linearity., , , and . APCCAS (1), page 1-4. IEEE, (2002)