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Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study.

, , , , , and . ISVLSI, page 731-736. IEEE Computer Society, (2016)

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Test Considerations about the Structured ASIC Paradigm., and . DDECS, page 232-233. IEEE Computer Society, (2006)Parallel Multithread Analysis of Extremely Large Simulation Traces., , , , , , and . IEEE Access, (2022)An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis., and . IEEE Trans. Instrum. Meas., 61 (4): 1002-1018 (2012)Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures., , , , , , , and . DDECS, page 69-74. IEEE, (2021)Exploring the Mysteries of System-Level Test., , , , , , , , , and . CoRR, (2021)An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 570-574 (2008)Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test., , , , and . J. Electron. Test., 30 (3): 317-328 (2014)A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques., , , , , , and . J. Electron. Test., 20 (1): 79-87 (2004)An Optimized Test During Burn-In for Automotive SoC., , , , , , , and . IEEE Des. Test, 35 (3): 46-53 (2018)Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs., , , , , and . VLSI-SoC (Selected Papers), volume 508 of IFIP Advances in Information and Communication Technology, page 130-151. Springer, (2016)