( en | de | ru )

 

Disambiguation of "Pétrot, Frédéric"

Author of the publication

copydeleteadd this publication to your clipboard
Virtual prototyping of floating point units.

, , and . RAPIDO@HiPEAC, page 1:1-1:6. ACM, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Frédéric Ruckert

Frédéric Robin

Frédéric Roux

Frédéric Leroux

Frédéric Ziebarth

 

Other publications of authors with the same name

Evaluation of the implementation cost of cache coherence protocols using omniscient actions., and . Des. Autom. Embed. Syst., 14 (1): 21-42 (2010)Native Simulation of MPSoC Using Hardware-Assisted Virtualization., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (7): 1074-1087 (2012)Toward Practical 128-Bit General Purpose Microarchitectures., , and . IEEE Comput. Archit. Lett., 22 (2): 81-84 (July 2023)Intégration sur plate-forme matérielle/logicielle de spécifications 'C' parallèles., , , and . Ann. des Télécommunications, 59 (7-8): 807-837 (2004)Loop aware IR-level annotation framework for performance estimation in native simulation., and . ASP-DAC, page 220-225. IEEE, (2017)Facing ADAS validation complexity with usage oriented testing., , , , , , , , and . CoRR, (2016)Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces., , and . DAC, page 366-375. ACM, (2012)Message-Oriented Devices on FPGAs., , , and . RSP, page 8-14. IEEE, (2018)Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors., and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 38-49. Springer, (2011)Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation., and . DATE, page 266-269. IEEE, (2017)