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Towards a sub-2.5V, 100-Gb/s Serial Transceiver., , , , , , , , and . CICC, page 471-478. IEEE, (2007)A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links., , , , , and . CICC, page 471-474. IEEE, (2008)A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS., , , , , and . ISSCC, page 180-181. IEEE, (2008)A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link., , , , , and . IEEE J. Solid State Circuits, 44 (8): 2085-2099 (2009)Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS., , , , , and . IEEE J. Solid State Circuits, 42 (7): 1564-1573 (2007)A 2.4-Vpp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies., , and . IEEE J. Solid State Circuits, 46 (10): 2226-2239 (2011)A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75Ω Coaxial Cable., and . IEEE J. Solid State Circuits, 43 (10): 2177-2186 (2008)A B-s complement continuous valued digit adder., , , , and . ICECS, page 433-436. IEEE, (2002)