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From Y-chart to seamless integration of application design and performance simulation., , , and . SoC, page 18-25. IEEE, (2010)Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile., , and . DSD, page 251-254. IEEE Computer Society, (2010)System-Level Modeling of Dynamically Reconfigurable Co-processors., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 881-885. Springer, (2004)Multi-threading support for system-level performance simulation of multi-core architectures., , , and . ARCS Workshops, VDE-Verlag, (2011)System Level Performance Simulation of Distributed GENESYS Applications on Multi-core Platforms., , , and . DASC, page 313-320. IEEE Computer Society, (2011)Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models., , and . EUROMICRO, page 172-181. IEEE Computer Society, (1997)Boundary Scan Testing Combined with Power Supply Current Monitoring., , and . EDAC-ETC-EUROASIC, page 232-235. IEEE Computer Society, (1994)System Level Architecture Exploration for Reconfigurable Systems On Chip., , , , , , and . FPL, page 1-6. IEEE, (2006)Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study., , , and . EURASIP J. Embed. Syst., (2008)Application Workload and SystemC Platform Modeling for Performance Evaluation., , , , , and . FDL (Selected Papers), volume 36 of Lecture Notes in Electrical Engineering, page 131-147. (2008)