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Disambiguation of "Shanbhag, Naresh R."

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Analytical Estimation of Transition Activity From Word-Level Signal Statistics.

, , and . DAC, page 582-587. ACM Press, (1997)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

An improved systolic architecture for 2-D digital filters.. IEEE Trans. Signal Process., 39 (5): 1195-1202 (1991)A pipelined adaptive NEXT canceller., and . IEEE Trans. Signal Process., 46 (8): 2252-2258 (1998)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (9): 726-730 (2014)High-speed architectures for Reed-Solomon decoders., and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 641-655 (2001)Joint Equalization and Coding for On-Chip Bus Communication., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 314-318 (2008)An In-Memory VLSI Architecture for Convolutional Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)A low-power bus design using joint repeater insertion and coding., and . ISLPED, page 99-102. ACM, (2005)Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers., and . ISLPED, page 334-339. ACM, (2001)Analytical Guarantees on Numerical Precision of Deep Neural Networks., , and . ICML, volume 70 of Proceedings of Machine Learning Research, page 3007-3016. PMLR, (2017)