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Engineering trust with semantic guardians.

, and . DATE, page 743-748. EDA Consortium, San Jose, CA, USA, (2007)

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Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (2): 380-393 (2008)Depth-driven verification of simultaneous interfaces., , and . ASP-DAC, page 442-447. IEEE, (2006)Post-Silicon Validation of Multiprocessor Memory Consistency., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (6): 1027-1037 (2015)An Effective Verification Solution for Modern Microprocessors.. University of Michigan, USA, (2008)Energy-efficient cache design using variable-strength error-correcting codes., , , , , and . ISCA, page 461-472. ACM, (2011)Testudo: Heavyweight security analysis via statistical sampling., , , , , , and . MICRO, page 117-128. IEEE Computer Society, (2008)Automatic error diagnosis and correction for RTL designs., , , and . HLDVT, page 65-72. IEEE Computer Society, (2007)Microprocessor Verification via Feedback-Adjusted Markov Models., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (6): 1126-1138 (2007)Caspar: Hardware patching for multicore processors., and . DATE, page 658-663. IEEE, (2009)Distributed hardware matcher framework for SoC survivability., and . DATE, page 305-310. IEEE, (2011)