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Disambiguation of "Scheuermann, Michael"

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Thermal analysis of multi-layer functional 3D logic stacks.

, , , , , , , , and . 3DIC, page 1-4. IEEE, (2016)

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Michael Scheuermann

Bernd Scheuermann

Walter Scheuermann

Wolfgang Scheuermann

Bernhard Scheuermann

 

Other publications of authors with the same name

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias., , , and . ISSCC, page 186-187. IEEE, (2012)IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors., , , , , , , , , and 21 other author(s). IBM J. Res. Dev., 62 (2/3): 10:1-10:14 (2018)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)Thermal analysis of multi-layer functional 3D logic stacks., , , , , , , , and . 3DIC, page 1-4. IEEE, (2016)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Design, CAD and technology challenges for future processors: 3D perspectives., , , , , and . DAC, page 212. ACM, (2011)